Highly available and reliable fault-tolerant systems, such as those used in telecommunications, web servers and highly-available storage systems rely on built-in diagnostics to automatically detect actual or impending failures. Once a problem is identified, the system can respond in providing a resolution or alternate path to prevent an outage of service to the customer. Traditionally, software-based functional tests were used to provide diagnostics that were built into a system and were usually provided by highly skilled programmers, who understood the internal workings of the circuits. These diagnostic systems require problem resolution granularity to the smallest field replaceable unit (FRU) that may be isolated for recovery. In the past, these FRUs were typically a single circuit board or a set of circuit boards.
Due to the increasing miniaturization of today, a single circuit board may contain specialized ASIC and programmable gate array devices. Each of these embody a level of functionality that would have required one or more complete circuit boards to implement, in the past. Further, many single circuit boards today contain multiple such devices thereby providing what an entire system provided in the past. Scaling the traditional approach for system diagnostics required for past systems to the complexity of current and projected future systems becomes increasingly problematic, especially when attempting to provide a product under a required market window constraint.
Boundary scan (JTAG) techniques and components employing the IEEE 1149.1 standard governing design, registers, protocols and testing of boundary scan components are generally used today. System level boundary scan testing, using a multi-drop architecture and a simplex or duplex test controller, is able to test any circuit board (i.e., a unit under test (UUT)) that is connected to a backplane. However, the issue of test vector management provides an ongoing difficulty. For each slot in a backplane, there may be a variety of versions of a circuit board or a multiplicity of specialized boards. Boundary scan tests are based on the specific structure of the circuit design. Thus, a test developed for one version of circuit board will not usually work properly for another version of the design. Therefore, a major testing difficulty is one of correctly selecting the appropriate test vectors, required by the test controller, for application to the UUT circuit board currently located in the test slot.
Many methods have been used to manage test vector selection including obtaining the vectors from the UUT by using existing application side system data busses, specialized state synchronization busses, maps of UUT ID codes to vector files that are either resident or downloaded to the test controller, and dedicated configurations per backplane slot. The retrieval of data using the existing application side system data busses tends to use more than fifty percent of the UUT circuits to perform the operation. Thus, the advantage of performing the Boundary Scan test is low and not cost effective since most of the circuit has already been tested by the retrieval operation. This also applies to the use of synchronization busses. Maps of ID codes to test data require services to be operational on the UUT to obtain the code, as well as a large data store on the test controller or download server for all possible versions. This latter approach also suffers from difficulties in managing version upgrades in the field, when new circuit boards are integrated into an existing system.
Accordingly, what is needed in the art is an enhanced way to ensure that the correct version of test vectors is applied to a specific UUT.